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You are here: Home / Topics / DESIGNING A FUZZY LOGIC CONTROLLER USING VHDL

DESIGNING A FUZZY LOGIC CONTROLLER USING VHDL

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Miscellaneous › Others › DESIGNING A FUZZY LOGIC CONTROLLER USING VHDL

  • This topic has 1 reply, 2 voices, and was last updated 10 years, 9 months ago by Ashutosh Bhatt.
Viewing 2 posts - 1 through 2 (of 2 total)
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    Posts
  • July 18, 2014 at 3:35 pm #3172
    kaburu kiragu
    Participant

    Hi,

    I have been trying to create a Very High speed integrated Description Language (VDHL) code that can implement a fuzzy logic controller.

    The controller has two inputs, 1) the error in temperature and 2) the change in error in temperature. The output is the voltage that controls the speed of a motor-driven fan.

    The VDHL code that i have so far developed generates a syntax error when compiled using the Xilinx ISE Project Navigator. Kindly assist me in degugging the code.

    The following is the VHDL code:


    — Company: 
    — Engineer: 
    — 
    — Create Date:    05:29:57 07/09/2014 
    — Design Name: 
    — Module Name:    air_conditioning – Behavioral 
    — Project Name:
    — Target Devices: 
    — Tool versions: 
    — Description: 
    —
    — Dependencies: 
    —
    — Revision: 
    — Revision 0.01 – File Created
    — Additional Comments: 
    —

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
     
    — Uncomment the following library declaration if using
    — arithmetic functions with Signed or Unsigned values
    –use IEEE.NUMERIC_STD.ALL;
     
    — Uncomment the following library declaration if instantiating
    — any Xilinx primitives in this code.
    –library UNISIM;
    –use UNISIM.VComponents.all;
     
    entity air_conditioning is
        Port ( Temp_error : in  STD_LOGIC_VECTOR (8 downto 0);
               Temp_change in error : in  STD_LOGIC_VECTOR (8 downto 0);
               Fan : out  STD_LOGIC_VECTOR (8 downto 0));
    end air_conditioning;
     
    architecture Behavioral of air_conditioning is
    type membership is (term, none);
    type mfs is record
    linguistic: membership;
    point1: std_logic_vector(7 downto 0);
    slope1: std_logic_vector(7 downto 0);
    point2: std_logic_vector(7 downto 0);
    slope2: std_logic_vector(7 downto 0); end record;
    type membership_functions is array(natural range <>) mfs;
    constant linguistic_name : membership_functions :=((linguistic => term, point1 => x”04″,
    slope1 => x”7F”, point2 => x”09″, slope2 => “55”), linguistic => none, point1 => x”FF”,
    slope1 => x”FF”, point2 => x”FF”, slope2 => x”FF”));
     
    type te_type is (cold, cool, mild, warm, hot, none); type te_ membership is record term: te_type;
    point1: std_logic_vector(7 downto 0); slope1: std_logic_vector(7 downto 0);
    point2: std_logic_vector(7 downto 0); slope2: std_logic_vector(7 downto 0);end record;
    type te_membership_functions is array(natural range <>) te_membership;
    constant te_mfs: te_membership_functions :=
    ((term => cold, point1 => x”00″, slope1 => x”FF”, point2 => x”2A”, slope2 => x”06″), (term
    => cool, point1 => x”2A”, slope1 => x”06″, point2 => x”55″, slope2 => x”06″), (term =>
    mild, point1 => x”55″, slope1 => x”06″, point2 => x”7F”, slope2 => x”06″),
    (term => warm, point1 => x”7F”, slope1 => x”06″, point2 => x”AA”, slope2 => x”06″),
    (term => hot, point1 => x”AA”, slope1 => x”06″, point2 => x”D5″, slope2 => x”FF”),
    (term => none, point1 => x”FF”, slope1 => x”FF”, point2 => x”FF”, slope2 => x”FF”));
     
    type tr_type is (slow, moderate, fast); type tr_ membership is record term: tr_type;
    point1: std_logic_vector(7 downto 0); slope1: std_logic_vector(7 downto 0);
    point2: std_logic_vector(7 downto 0); slope2: std_logic_vector(7 downto 0); end record;
    type tre_membership_functions is array(natural range <>) tr_membership;
    constant tr_mfs: tr_membership_functions :=
    ((term => slow, point1 => x”00″, slope1 => x”00″, point2 => x”32″, slope2 => x”03″),
    (term => moderate, point1 => x”32″, slope1 => x”03″, point2 => x”7E”, slope2 => x”03″),
    (term => fast, point1 => x”7E”, slope1 => x”03″, point2 => x”FF”, slope2 => x”FF”),
    (term => none, point1 => x”FF”, slope1 => x”FF”, point2 => x”FF”, slope2 => x”FF”));
     
    constant very_low : std_logic_vector := x”2A”; constant low : std_logic_vector := x”55″;
    constant medium : std_logic_vector := x”7F”; constant high : std_logic_vector := x”A8″;
    constant very_high : std_logic_vector := x”D2″;
    type singletons is array (0 to 4) of std_logic_vector(7 downto 0);
    signal ac : singletons := (very_low, low, medium, high, very_high);
     
    Rule 1: very_high <= minimum(cold, fast);
    Rule 2: high <= minimum(cold, slow);
    Rule 3 and Rule 4: medium <= maximum( minimum(cool, moderate), minimum(mild, slow));
    Rule 5 and Rule 6: low <= maximum( minimum(warm, slow), minimum(warm, moderate));
    Rule 7 and Rule 8: very_ low <= maximum( minimum(hot, slow), minimum(hot, fast));
     
    begin
    Set n = number of membership function = 13; Set µ = array of degree of membership function = 2;
    Set membership = array of membership function; For i = 1 to n do begin
    if input value < membership.point 1 then µ = 0;
    else if input value < membership.point 2 then
    µ = (input value – membership.point 1) × membership.slope 1;
    else µ = 255 – (input value – membership.point 2) × membership.slope 2;
    end if; end for loop;
     
    Defuzzification():
    Set n = number of output membership function = 13; Set s = array of singleton of output = 2
    membership function; Set f = array of result of all rule evaluations; Set sum = 0
    For i = 1 to n do begin product = (s(i) × f(i)) + product; sum = f + sum; end for loop;
    output = product / sum;
     
    end Behavioral;
     
    Yourfaithfully,
    Mike Wachira
     

     

    July 23, 2014 at 6:26 am #11923
    Ashutosh Bhatt
    Participant

    thanks for posting question on this website

    you will get more help on this if you post it on XILINX forum because you are using xilinx’s ISE software tools.

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