confusion regarding the timing diagram for bit from slave in I2C

[sayonee3]

Hello there I am newbie

I have confusion about the timing diagram for I2C.Whenever a byte is sent to the slave by MC(master) and after receiving the ACK the slave would send a byte …at this moment the timing diagram is supposed to be different than when the master is sending to slave

When the master sends to slave a byte all bits are transmitted on the rising edge of SCL
But when the master is receiving from slave the bits are received on the falling edge of the SCL is..this correct I am confused sine there are websites that mention that the working of master receiving the data is similar to master sending the data to slave

I was reading this one tutorial about interfacing an EEPROM using I2C and couldn’t understand as to why the data is valid from the falling edge when bit is transmitted from slave(EEPROM) to Microcontroller….

here is the link http://www.engineersgarage.com/microcontroller/8051projects/interface-serial-eeprom-24c02-AT89C51-circuit#tabset-tab-9

Please let me know with explanation and some more links and sources

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